In IC manufacturing, lithography is an essential process step. Due to the continuous reduction in feature sizes, optical proximity correction (OPC) techniques are deployed to calculate what photomask pattern should be deployed to create the desired wafer pattern. The switch to heavily-OPCed patterns is computationally challenging, but also brings certain challenges for masks and their fabrication. Therefore, advanced masks should be fabricated to enable the patterning of reduced feature sizes.
In addition to the main design features, sub resolution assist features (SRAF) are typically present on masks to improve the printability of design features. When the mask is exposed by the light from the source, light is blocked completely by the larger design features. The smaller assist features partially block the light and do not image on the substrate to be patterned. The final substrate pattern can achieve better performance because of these assist features.
Advanced masks require very small features (<10 nm on mask) that are beyond the resolution limits of mask fabrication methods. Adding the small features forces the e-beam patterning systems to generate very small e-beam “shots” that dramatically increase write time in such beams. In order to write these small assist features, they must exist in the mask data and this explodes the data volume—for example—increasing data volume from ˜50 Mb at 65 nm logic nodes to over 150 Gb at 7 nm logic nodes. Complex models must be created and calibrated to design and add such small assist features that can make the mask fabrication process quite cumbersome.
Therefore, there is a need in the art for methods to manufacture masks without increasing data volume and/or without increasing write-time on the state-of-the-art scan beams.